Steven F. Hoover
36 Venus Drive
Shrewsbury, MA 01545
OBJECTIVE: Computer Architecture and Chip Design Methodology R&D
- President of Redwood EDA; inventor and developer of chip design technology that is poised to redefine the industry.
- Over 18 years of experience designing and verifying server chips and delivering to aggressive schedules and design goals through architecture, tool, and methodology innovation as well as execution.
- Proficiency with many programming languages and environments.
- Entrepreneurship and leadership experience.
- Strong academic foundation.
Redwood EDA, MA. [Nov. 2014 - present]
- Spearheading the evolution of Transaction-Level Verilog (TL-Verilog) which incorporates transaction-level abstractions into SystemVerilog while retaining RTL-level control over their implementation. TL-Verilog boasts code reductions on the order of 6x versus SystemVerilog for High-Level Models. These can be evolved to generate production RTL with a 2x source code reduction, significantly accelerating the design cycle.
- Developing and productizing SandPiper™, a code generator that quickly translates TL-Verilog to readable SystemVerilog.
Logic Design Lead
Intel Corporation, Massachusetts Microprocessor Design Center, Hudson, MA. [Aug. 2001 – Oct. 2014]
- Led the logic design effort of a second-generation switch for Intel’s Omni Scale Fabric Architecture. Coordinated efforts with the architecture, validation, implementation, design automation, and reliability teams. Contributed significantly to the architectural definition and explored implementation tradeoffs to refined the microarchitecture. Defined much of the project’s front-end design methodology, incorporating SoC tools and methods as well as introducing new capabilities, in preparation for model development.
- Participated in several division-level technical steering work groups, defining future design methodology direction for Intel's server products.
- Invented and led development of design methodology that provided the foundation for TL-Verilog.
- Co-owned the on-chip power delivery solution for a Xeon server CPU.
- Owned the microarchitecture and logic design of a memory-side cache controller for a design targeting HPC applications.
- Developed post-silicon system and tester power strategy and content for Poulson, an Itanium Processor Family CPU.
- Led a six-person design team delivering directory-based cache coherence and memory controller logic for Poulson.
- Developed an RTL conversion and resynchronization methodology and flow, enabling efficient leveraging of changing code in a different RTL language.
- Was awarded for developing an RTL hierarchy connectivity tool, addressing a critical program bottleneck.
- Microarchitected the indirect branch predictor, return stack, register renamer, register stack engine, and speculative state maintenance logic for an Itanium Processor Family microprocessor.
- Engineered the verification build/versioning environment for a cross-site Itanium Processor Family microprocessor project.
Senior Hardware Engineer
Compaq Computer Corporation (formerly Digital Equipment Corporation), Modeling Tools and Verification Group, Shrewsbury, MA. [Aug. 1996 - Aug. 2001]
- Led functional verification of the out-of-order core of the Alpha 21464 AXP (EV8) microprocessor, and later, of the simultaneous multithreading functionality.
- Launched and headed development of SimView -- a generic simulation visualization tool, written in C++, and used heavily in verifying EV8.
- Engineered an infrastructure for an ISA-level Alpha test suite, including incorporating higher-level language constructs into an Alpha assembler. Supervised test developers, and used this test suite to verify existing RTL models for multiple Alpha projects.
- Six invention disclosures for indirect branch prediction and switch architecture.
- Three publications, internal to Intel, on design methodology.
- 12 Division, Department, and Team recognition awards for project delivery, eliminating barriers, and improving efficiency.
University of Illinois
Master of Computer Science, May 1996
Honors and Appointments:
- University Fellowship.
- Tau Beta Pi Fellowship.
- Teaching Assistantship for Intro. to Parallel Programming. [Jan. 1996 - May 1996]
- Research Assistantship in the Concurrent Systems Architecture Group, under Dr. Andrew Chien, introducing new paradigms of medium- and fine-grained parallel computing on workstation clusters. [Jan. 1995 - Jan. 1996]
Rensselaer Polytechnic Institute
BS in Electrical Engineering, May 1994
Numerous awards, honors, and scholarships.
- RTL Development: TL-Verilog (inventor), SystemVerilog (subset of TL-Verilog), VHDL (and several proprietary languages).
- Code Management: Git, BitKeeper, Vesta, Make, RCS, CVS.
References Available Upon Request.